sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 options marking ? timing 30ns access -30 ? package(s) ceramic dip (400 mil) c no. 111 ? temperature military (-55c to +125c) mil ? options 2v data retention/very low power ll pin assignment (top view) available as military specifications ?mil-std-883, para. 1.2.2 compliant 32-pin dip (c) general description the mt5c1008 sram is a high-performance cmos static ram organized as 131, 072 words by 8 bits, offering low active power and ultra low standby and data retention current levels. easy memory expansion is provided by an active low chip enable (ce1\), an active high chip enable (ce2), and active low output enable (oe\), and three-state drivers. writing to the device is accomplished by taking chip enable one (ce1\) and write enable (we\) inputs low and chip enable two (ce2) input high. data on the eight i/o pins (i/o0 through i/o7) is then written into the location specified on the address pins (a0 through a16). reading from the device is accomplished by taking chip enable one (ce 1 \) and output enable (oe\) low while forcing write enable (we\) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output (i/o0 through i/o7) are placed in a high-impedance state when the device is deselected (ce1\) high or ce2 low), the outputs are disabled (oe\ high), or during a write operation (ce1\ low, ce2 high, and we\ low). 128k x 8 sram with dual chip enable ultra low power features ? high speed: 30 ns ? low active power: 715 mw worst case ? low cmos standby power: 3.3 mw worst case ? 2.0v data retention, ultra low 0.3mw worst case power dissipation ? battery backup applications ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce1\, ce2, and oe\ options nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd 32 31 30 29 28 26 27 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc a15 ce2 we\ a13 a8 a9 a11 oe\ a10 ce1\ i/o7 i/o6 i/o5 i/o4 i/o3 for more products and information please visit our web site at www.austinsemiconductor.com
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table mode oe\ ce1\ ce2 we\ i/o0 - i/o7 power power-down x h x x high z standby (i sb ) power-down x x l x high z standby (i sb ) read l l h h data out active (i cc ) write x l h l d ata in active (i cc ) selected, outputs disabled h l h h high z active (i cc )
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* supply voltage range on vcc to relative gnd 1 ..-0.5v to +7.0v storage temperature .............................................-65 c to +150 c ambient temperature with power applied........-55c to +125c dc voltage applied to outputs in high z state 1 .................................................-0.5v to vcc + 0.5v dc input voltage 1 .............................................-0.5v to vcc + 0.5v *stresses at or greater than those listed under "absolute maxi- mum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods will affect reliability. refer to page 17 of this data sheet for a technical note on this subject. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. parameter conditions sym min max units notes output high voltage vcc = min, i oh = -4.0 ma v oh 2.4 v output low voltage vcc = min, i ol = 8.0 ma v ol 0.4 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il -0.3 0.8 v 1 input load current gnd < v i < vcc i ix -10 +10 a output leakage current gnd < v i < vcc, output disabled i oz -10 +10 a vcc operating supply current vcc = max, i out = 0 ma f = f = 1/t rc i cc 130 ma automatic ce power- down current - ttl inputs max vcc, ce1\ > v ih or ce2 < v il , v in > v ih or v in < v il , f = f max i sb1 4ma automatic ce power- down current - cmos inputs max vcc, ce1\ > vcc - 0.3v, or ce2 < 0.3v, v in > vcc - 0.3v, or v in < 0.3v, f = 0 i sb2 0.6 ma -30 electrical characteristics and recommended operating conditions (-55 o c < t c < 125 o c; v cc = 5.0v +10%) notes: 1. vil(min) = -2.0v for pulse durations of less than 20ns.
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 ac test loads and waveforms capacitance 1 parameter conditions sym max units input capacitance (a0 - a16) c in 8pf input capacitance (ce\, we\, oe\) c clk 10 pf output capacitance c out 12 pf ta = 25c, f = 1mhz, vcc = 5.0v data retention characteristics (-55 o c < t c < 125 o c; v cc = 5.0v +10%) parameter conditions sym min max units vcc for data retention v dr 2.0 v data retention current i ccdr 150 a chip deselect to data retention time t cdr 0ns operation recovery time t r 200 s 0.2v, vcc = v dr = 2.0v, ce1\ > vcc - 0.3v or ce2 < 0.3v, v in > vcc - 0.3v or v in < 0.3v notes: 1. tested initially and after any design or process changes that may effect these parameters. data retention waveform
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 notes: 1. test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30pf load capacitance. 2. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5pf as in part (b) of ac test loads. transition is measured 500mv from steady-state voltage. 3. at any given temperature and voltage condition, t hzce < t lzce , t hzoe < t lzoe , and t hzwe < t lzwe for any given device. 4. the internal write time of the memory is defined by the overlap of ce1\ low, ce2 high, and we\ low. ce1\ and we\ must be lo w and ce2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 5. the minimum write cycle time for write cycle no. 3 (we\ controlled, oe\ low) is the sum of t hzwe and t sd . switching characteristics 1 (-55 o c < t c < 125 o c; v cc = 5.0v +10%) parameter sym min max units notes read cycle time t rc 30 ns address to data valid t aa 30 ns data hold from address change t oha 3ns ce1\ low to data valid, ce2 high to data valid t ace 30 ns oe\ low to data valid t doe 12 ns oe\ low to low z t lzoe 0ns oe\ high to high z t hzoe 8 ns 2, 3 ce1\ low to low z, ce2 high to low z t lzce 3ns3 ce1\ high to high z, ce2 low to high z t hzce 15 ns 2, 3 write cycle time t wc 30 ns 5 ce1\ low to write end, ce2 high to write end t sce 22 ns address set-up to write end t aw 22 ns address hold from write end t ha 0ns address set-up to write start t sa 0ns we\ pulse width t pwe 22 ns data set-up to write end t sd 18 ns data hold from write end t hd 0ns we\ high to low z t lzwe 5ns3 we\ low to high z t hzwe 8 ns 2, 3 -30 read cycle write cycle 4
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 switching waveforms read cycle no. 1 1,2 read cycle no. 2 (oe\ controlled) 2,3 notes: 1. device is continuously selected. oe\, ce1\ = v il , ce2 = v ih . 2. we\ is high for read cycle. 3. address valid prior to or coincident with ce1\ transition low and ce2 transition high.
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 switching waveforms (continued) write cycle no. 1 (ce1\ or ce2 controlled) 1,2 write cycle no. 2 (we\ controlled, oe\ high during write) 1,2 notes: 1. data i/o is high impedance if oe\ = vih. 2. if ce1\ goes high or ce2 goes low simultaneously with we\ going high, the output remains in a high-impedance state. 3. during this period the i/os are in the output state and input signals should not be applied.
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 notes: 1. if ce1\ goes high or ce2 goes low simultaneously with we\ going high, the output remains in a high-impedance state. 2. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) write cycle no. 3 (we\ controlled, oe\ low) 1
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 mechanical definitions* asi case #111 (package designator c) *all measurements are in inches. d s1 pin 1 se b b1 a s2 q l l1 c note e 0 o to 15 o e1 min max a --- 0.232 b 0.014 0.023 b1 0.038 0.065 c 0.008 0.015 d --- 1.700 e 0.350 0.405 e1 0.390 0.420 e 0.100 bsc l 0.125 0.200 l1 0.150 --- q 0.015 0.060 s --- 0.100 s1 0.005 --- s2 0.005 --- symbol asi specifications note: either confi g uration in detail a is allowed. detail a
sram sram sram sram sram mt5c1008(ll) ultra low power austin semiconductor, inc. mt5c1008(ll) rev. 1.0 7/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 *available processes mil = military processing (mil-std-883, para. 1.2.2 compliant) -55 o c to +125 o c ** options ll = 2v data retention/ultra low power note: for other speeds and options, see the mt5c1008 data sheet (available from www.austinsemiconductor.com). ordering information example: mt5c1008c-30ll/mil device number package t yp e speed ns options** process mt5c1008 c -30 ll /*
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